98.10.26上課練習

module top;
wire A1,A0,B1,B0;
system_clk #50 clk1(B0);
system_clk #100 clk2(B1);
system_clk #200 clk3(A0);
system_clk #400 clk4(A1);
comparator c1 (A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
endmodule


module comparator(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
input A1,A0,B1,B0;
output A_lt_B,A_gt_B,A_eq_B;
assign A_lt_B = (~A1)&B1(~A1)&(~A0)&B0(~A0)&B1&B0;
assign A_gt_B = A1&(~B1)A0&(~B1)&(~B0)A1&A0&(~B0);
assign A_eq_B = (~A1)&(~A0)&(~B1)&(~B0)(~A1)&A0&(~B1)&(~B0)A1&A0&B1&(~B0)A1&(~A0)&B1&(~B0);
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

98.10.05上課練習

module top;
integer ia,ib;
reg a,b;
wire s,c;
and a1(c,a,b);
xor x1(s,a,b);
initial
begin
for(ia=0;ia<=1;ia=ia+1) begin a=ia; for(ib=0;ib<=1;ib=ib+1) begin b=ib; #10 $display("a=%d b=%d c=%d s=%d",a,b,c,s); end end end endmodule