98.11.30上課練習

module top;
wire o,A1;
system_clk #50 clk1(A1);
nanf201 c1 (o,A1);
endmodule

module nanf201(o,A1);
input A1;
output o;
not(o,A1);
specify
specparam
tpd_0_1=1.13:3.09:7.75,
tpd_1_0=0.93:2.5:7.34;
(A1=>o)=(tpd_0_1,tpd_1_0);

endspecify
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(49*period/50)clk=~clk;
#(period-49*period/50)clk=~clk;
end
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

98.11.16上課練習(三)

module top;
wire data_in,clk,set,rst;
system_clk #50 clk1(data_in);
system_clk #100 clk2(clk);
system_clk #200 clk3(set);
system_clk #400 clk4(rst);
flip_flop c1 (q,data_in,clk,set,rst);
endmodule

module flip_flop(q,data_in,clk,set,rst);
input data_in,clk,set,rst;
output q;
reg q;
always@(posedge clk)
begin
if(rst==0)q=0;
else
if(rst==0)q=1;
else
q=data_in;
end
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

98.11.16上課練習(2)

module top;
wire [3:0]x_in;
system_clk #50 clk1(x_in[0]);
system_clk #100 clk2(x_in[1]);
system_clk #200 clk3(x_in[2]);
system_clk #400 clk4(x_in[3]);
and4_rtl c1 (y_out,x_in);
endmodule

module and4_rtl(y_out,x_in);
input [3:0]x_in;
output y_out;
reg y_out;
integer k;
always @ (x_in)
begin: and_loop
y_out=0;
for(k=0;k<=3;k=k+1) if(x_in[k]==1) begin y_out=1; disable and_loop; end end endmodule module system_clk(clk); parameter period=100; output clk; reg clk; initial clk=0; always #(period/2)clk=~clk; always@(posedge clk)

98.11.16上課練習

module top;
wire [3:0] x_in;
system_clk #50 clk1(x_in[0]);
system_clk #100 clk2(x_in[1]);
system_clk #200 clk3(x_in[2]);
system_clk #400 clk4(x_in[3]);
and4_algo c1 (y_out,x_in);
endmodule

module and4_algo (y_out,x_in);
input [3:0] x_in;
output y_out;
reg y_out;
integer k;
always@(x_in)
begin:and_loop
y_out=1;
for(k=0;k<=3;k=k+1) if(x_in[k]==0) begin y_out=0; disable and_loop; end end endmodule module system_clk(clk); parameter period=100; output clk; reg clk; initial clk=0; always #(period/2)clk=~clk; always@(posedge clk) if($time>1000)
#(period-1)
$stop;
endmodule

98.11.09上課練習(2)

module top;
wire [3:0] x_in;
system_clk #50 clk1(x_in[0]);
system_clk #100 clk2(x_in[1]);
system_clk #200 clk3(x_in[2]);
system_clk #400 clk4(x_in[3]);
and4_rtl c1 (y_out,x_in);
endmodule

module and4_rtl(y_out,x_in);
input [3:0] x_in;
output y_out;
assign y_out=&x_in;
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

98.11.09上課練習

module top;
wire x_in1,x_in2,x_in3,x_in4;
system_clk #50 clk1(x_in1);
system_clk #100 clk2(x_in2);
system_clk #200 clk3(x_in3);
system_clk #400 clk4(x_in4);
and4_rtl c1 (y_out,x_in1,x_in2,x_in3,x_in4);
endmodule

module and4_rtl(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
assign y_out=x_in1&x_in2&x_in3&x_in4;
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

98.10.26上課練習

module top;
wire A1,A0,B1,B0;
system_clk #50 clk1(B0);
system_clk #100 clk2(B1);
system_clk #200 clk3(A0);
system_clk #400 clk4(A1);
comparator c1 (A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
endmodule


module comparator(A_lt_B,A_gt_B,A_eq_B,A1,A0,B1,B0);
input A1,A0,B1,B0;
output A_lt_B,A_gt_B,A_eq_B;
assign A_lt_B = (~A1)&B1(~A1)&(~A0)&B0(~A0)&B1&B0;
assign A_gt_B = A1&(~B1)A0&(~B1)&(~B0)A1&A0&(~B0);
assign A_eq_B = (~A1)&(~A0)&(~B1)&(~B0)(~A1)&A0&(~B1)&(~B0)A1&A0&B1&(~B0)A1&(~A0)&B1&(~B0);
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

98.10.05上課練習

module top;
integer ia,ib;
reg a,b;
wire s,c;
and a1(c,a,b);
xor x1(s,a,b);
initial
begin
for(ia=0;ia<=1;ia=ia+1) begin a=ia; for(ib=0;ib<=1;ib=ib+1) begin b=ib; #10 $display("a=%d b=%d c=%d s=%d",a,b,c,s); end end end endmodule

98.09.28上課練習

module top;
integer ia,ib;
reg a,b;
wire c;
xor x1(c,a,b);
initial
begin
for(ia=0;ia<=1;ia=ia+1)
begin
a=ia;
for(i=0;ib<=1;ib=ib+1)
begin
b=ib;
#10 $display("a=%d b=%d c=%d",a,b,c);
end
end
end
end
module

98.09.21上課練習

module top;
wire a,b;
reg c;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
always
#1 c=a&b;
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initialclk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1) $stop;
endmodule