98.11.16上課練習(三)

module top;
wire data_in,clk,set,rst;
system_clk #50 clk1(data_in);
system_clk #100 clk2(clk);
system_clk #200 clk3(set);
system_clk #400 clk4(rst);
flip_flop c1 (q,data_in,clk,set,rst);
endmodule

module flip_flop(q,data_in,clk,set,rst);
input data_in,clk,set,rst;
output q;
reg q;
always@(posedge clk)
begin
if(rst==0)q=0;
else
if(rst==0)q=1;
else
q=data_in;
end
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule